The MachSuite Benchmark

I. INTRODUCTION With the demise of Dennard scaling, today's architects are confronting chips filled with more transistors than can be fully powered. One possible mechanism to continue improving performance on a power budget is the use of hardware accelerators , fixed-function hardware blocks which compute a specific task at a fraction of the cost of a general-purpose processor. Unfortunately, designing hardware accelerators in RTL languages like Verilog or VHDL is time-consuming and complicated. To improve productivity, the CAD community introduced High-Level Synthesis (HLS) tools, which automatically synthesize RTL code from a high-level language like C or C++. Modern HLS frameworks can produce code with performance on par with handwritten RTL for some workloads. However, as designers tackle more complicated, irregular applications, these tools are struggling. The interest in hardware specialization has brought about challenges at the architecture level as well. Fine-grained het-erogeneity has appeared in processors, and the rising popularity of systems-on-chip (SoCs) in the mobile domain is making hardware accelerators commonplace. Architects now have to contend with a much larger range of on-chip interactions, and with so many different possible tactics and mechanisms, it is a daunting task to choose the right design direction. These trends are two sides of the same coin: advances in accelerator-centric research have caught us unprepared to quantitatively and objectively evaluate the relative strengths and weaknesses of such a diverse collection of techniques. Much of this can be ascribed to a simple lack of standardization. A survey of recent publications involving hardware accelerators revealed that of the 88 distinct benchmarks used across 25 papers, 64 of them were only ever used once, as shown in Figure 1. The most popular benchmarks appeared in less than half of those. The community needs standardization and commensurability. Consequently, we present MachSuite 1 : a new accelerator-centric benchmark suite tailored to the needs of both the HLS and architecture communities. MachSuite is a set of 19 benchmarks spanning 12 different kernels, written to cover a diverse set of application domains and to incorporate distinct algorithmic choices. All the benchmarks in MachSuite are HLS synthesizable, providing architecture researchers an easy way to quickly generate a diverse set of hardware accelerators.